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A 12‐bit segmented resistor–capacitor digital‐to‐analog converter for a display driver IC of a large TFT‐LCD panel system
Author(s) -
Yoo Seongjong,
Song Yongjoo,
Jung Jiwoon,
Lee Myunghee
Publication year - 2009
Publication title -
information display
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.182
H-Index - 20
eISSN - 2637-496X
pISSN - 0362-0972
DOI - 10.1002/j.2637-496x.2009.tb00069.x
Subject(s) - least significant bit , resistor , differential nonlinearity , cmos , voltage , sample and hold , 8 bit , 12 bit , liquid crystal display , integral nonlinearity , digital to analog converter , capacitor , offset (computer science) , electrical engineering , channel (broadcasting) , bit (key) , computer science , electronic engineering , computer hardware , engineering , converters , operating system , computer security , programming language
A 12‐bit segmented R–C DAC to support a linear gamma curve has been proposed and fabricated in a 720‐channel LCD source driver with a 16‐V 1‐poly 3‐metal highvoltage CMOS process. The proposed DAC has a global resistor string and sample‐and‐hold buffers. A MSB voltage selected by the upper 6 bits of input data and a LSB voltage selected by the lower 6 bits of input data are summed by using a sample‐and‐hold operation with offset cancellation in the proposed DAC. The measured DNL was less than 0.3 LSB, and the output voltage deviation was less than 3 mV in all gray levels. Although two sample‐and‐hold buffers were adopted to operate alternatively, the die size was as small as 24.9 mm 2 , which was only an 8.3% increase compared to that of a conventional 8‐bit 720‐channel source driver. Because of its good performance with small area, the proposed DAC can be a good low‐cost solution for a 10‐bit TV system.