Premium
3.4.3 Generation of Hardware Description Languages from Modelisation tools based on Meta‐modelisation
Author(s) -
Rault Valéry
Publication year - 2003
Publication title -
incose international symposium
Language(s) - English
Resource type - Journals
ISSN - 2334-5837
DOI - 10.1002/j.2334-5837.2003.tb02642.x
Subject(s) - computer science , verilog , standardization , hardware description language , software engineering , code generation , software , programming language , vhdl , unified modeling language , computer architecture , generator (circuit theory) , embedded system , operating system , field programmable gate array , key (lock) , power (physics) , physics , quantum mechanics
One of the main problems when creating systems lies in the different tools and methods used by the various disciplines. Even when doing calculators and computers, with the involvement of only two disciplines, hardware and software, this situation raises many problems early in the design phase and has important consequences on the result. A way to break this wall would be to standardize the efforts around a single design tool, used by the systems, software and hardware engineers as well. As an enabler for such a standardization capability, this paper presents a generator of hardware description languages that uses a meta‐model. A major benefit is to generate code such as VHDL, Verilog or System C from various modelling tools like UML, I‐Logix's Statemate or even from other sources.