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3.2.2 Interfacing a Verification, Validation, and Testing Process Model with Product Development Methods
Author(s) -
Hoppe Markus,
Lévárdy Viktor,
Vollerthun Andreas,
Wenzel Stefan
Publication year - 2003
Publication title -
incose international symposium
Language(s) - English
Resource type - Journals
ISSN - 2334-5837
DOI - 10.1002/j.2334-5837.2003.tb02610.x
Subject(s) - interfacing , computer science , process (computing) , schedule , product (mathematics) , process validation , quality (philosophy) , reliability engineering , process management , verification and validation , operations management , engineering , philosophy , geometry , mathematics , epistemology , computer hardware , operating system
Abstract A thorough balancing of the costs of conducting verification and validation with the costs of failure promises new possibilities in reducing overall project costs and time‐to‐market. One goal of the presented SysTest project is to develop an approach to support the strategic verification, validation, and test (VVT) planning. This approach, reflected in the VVT Process Model, supports the trade off between different VVT strategies by calculating the effect of the strategy on cost‐, schedule‐, and quality‐risk. This paper describes the VVT Process Model, which is currently developed, and its application in the development process of a hydraulic pump. Furthermore, its interfaces with other company methods and the corresponding information flows between them are illustrated. To demonstrate its potential, the VVT Process Model is positioned in the verification process.