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P‐24: IGZO‐TFT Based Latch Circuit with High Stability and Full‐Swing Output for System‐on‐Panel †
Author(s) -
Liao Congwei,
Hu Zhijin,
Li Wenjie,
Li Junmei,
Zhang Shengdong
Publication year - 2014
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2014.tb00268.x
Subject(s) - swing , thin film transistor , transistor , voltage , logic gate , electrical engineering , materials science , electronic engineering , optoelectronics , computer science , engineering , nanotechnology , mechanical engineering , layer (electronics)
This paper presents an IGZO‐TFT latch circuit featuring high stability and simple structure with only 5 TFTs per stage. Pass‐transistor logic style with gate voltage bootstrapped is used to suppress voltage amplitude loss and achieve a full swing output. Comparison studies are carried out with conventional latch, and results show that the proposed one has compact layout, free DC stress and enhanced immunity to △V TH .