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P.64: WITHDRAWN: P.65: The Effect of Surface Polarity of Gate Dielectric Buffer Layer on Operational Stability in Organic Thin Film Transistors
Author(s) -
Roh Jeongkyun,
Kang Chanmo,
Shin Hyeonwoo,
Kwak Jeonghun,
Jung Byung Jun,
Lee Changhee
Publication year - 2013
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2013.tb06455.x
Subject(s) - pentacene , polarity (international relations) , materials science , thin film transistor , gate dielectric , optoelectronics , threshold voltage , transistor , layer (electronics) , dielectric , buffer (optical fiber) , organic electronics , electrical engineering , chemistry , nanotechnology , voltage , biochemistry , engineering , cell
We studied the effect of surface polarity of gate dielectric buffer layer on operational stability in organic thin film transistors (OTFTs). By employing four types of polymers with different polarity, we found out the operational stability of OTFTs can be improved with low‐polarity polymer gate dielectric buffer layer. With low‐polarity polymers, the devices showed good operational stability with longer relaxation time than 10 6 sec. Also, threshold voltage of the devices shifted less than 2 V under high gate bias stress of 3 MV/cm for two hours. Good stability may be resulted from low surface trap density as well as good grain interconnection of pentacene on low‐polarity polymer.