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31.4: A 3.4Gbps/lane Low Overhead Clock Embedded Intra‐panel Interface for High Resolution and Large‐Sized TFT‐LCDs
Author(s) -
Oh WoonTaek,
Kim JinHo,
Chang YoungHwan,
Kim TeaJin,
Lee JaeYoul,
Nah KyungSuc,
Hwang GyooCheol
Publication year - 2013
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2013.tb06230.x
Subject(s) - interface (matter) , computer science , frame (networking) , overhead (engineering) , computer hardware , flash memory , embedded system , jitter , real time computing , computer network , telecommunications , operating system , bubble , maximum bubble pressure method
This paper proposes a 3.4Gbps/lane intra‐panel interface with 11.1% of the protocol overhead for the raw data to be transmitted. The proposed intra‐panel interface uses a point‐to‐point interface architecture with embedded clock. To reduce the EMI radiation, the scrambling scheme was adopted. The protocol of the proposed intra‐panel interface provides a PLL based clock and data recovery (CDR) scheme for the receiver. Timing controller (TCON) and source driver (SD) are implemented using 45nm/1.1V and 0.18um/1.8V CMOS processes, respectively. The proposed interface is verified on a 55‐inch Full‐HD TFT‐LCD panel with 8bit RGB and 120‐Hz frame rates. The maximum data rate per lane was measured as up to 3.4Gbps/lane.