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31.3: A 10‐bit CMOS Digital‐to‐Analog Converter with Logarithmic Time Interpolation
Author(s) -
Kim Mungyu,
Chung HoonJu,
Jang YoungChan
Publication year - 2013
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2013.tb06229.x
Subject(s) - least significant bit , 12 bit , 8 bit , bit (key) , digital to analog converter , differential nonlinearity , cmos , logarithm , interpolation (computer graphics) , resistor , amplifier , computer science , operational amplifier , analog to digital converter , electronic engineering , electrical engineering , mathematics , computer hardware , voltage , engineering , telecommunications , frame (networking) , mathematical analysis , computer security , operating system
A 10‐bit logarithmic time interpolation digital‐to‐analog converter (DAC) which consists of a 7‐bit resistor string, a 7‐bit two‐step decoder, a 2‐bit logarithmic time interpolator, and a buffer amplifier is proposed for data‐driver integrated circuits of active‐matrix liquid crystal display systems. It occupies 57% of the area of the conventional 10‐bit resistor‐string DAC. The DNL and INL of the implemented 10‐bit DAC were +0.29/‐0.30 and +0.47/‐0.36 LSB, respectively, where 1 LSB is equal to about 4.5 mV.