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P‐45: A 2.4Gbps Receiver with Bang‐Bang CDR for High Speed Intra‐Panel Interface
Author(s) -
Kim TaeJin,
Oh WoonTaek,
Kim JinHo,
Ihm JaeYong,
Chang Yonghwan,
Lee JaeYoul,
Lee Myunghee
Publication year - 2012
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2012.tb06019.x
Subject(s) - interface (matter) , phase locked loop , signal (programming language) , scrambling , computer science , electronic engineering , jitter , engineering , algorithm , bubble , maximum bubble pressure method , parallel computing , programming language
A Receiver incorporating bang‐bang (binary) CDR for high speed intra panel interface is proposed. The proposed Receiver adopting Phase Locked Loop (PLL) based CDR provides high speed data rate by a bang‐bang Phase Detector and Current Mode Logic (CML). Also it provides low EMI for LCD system by embedding the clock signal without explicit clock lines and scrambling active data. The results are validated on a 55‐inch full‐HD (1920×1080) TFT‐LCD panel with the 8‐bit RGB and 120Hz driving technology. Maximum data rate is measured as higher than 2.4Gbps.