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P‐42: Skew‐less Point‐to‐Point Mini‐LVDS (SPPmL) Interface for Large‐Scale TFT‐LCD Applications
Author(s) -
Huang WenChiang,
Chung ChunFan,
Yang ChihHsiang,
Ho YuHsi,
Chang RongYuan
Publication year - 2012
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2012.tb06016.x
Subject(s) - skew , computer science , interface (matter) , controller (irrigation) , phase locked loop , clock signal , liquid crystal display , synchronization (alternating current) , signal (programming language) , computer hardware , transfer (computing) , electronic engineering , engineering , jitter , parallel computing , telecommunications , channel (broadcasting) , bubble , maximum bubble pressure method , agronomy , biology , programming language , operating system
This paper presents an intra‐panel interface that adopts a skew‐less point‐to‐point mini‐LVDS (SPPmL) using 240 Hz of driving technology. A differential data signal with an embedded code was applied between the timing controller (TCON) and column driver ICs (DICs) to synchronize the clock and data. The synchronization core circuit was based on a delay cell that eliminates clock and data skew problems. Power consumption was effectively reduced using a delay cell circuit lower than using a phase‐locked loop (PLL) and a delay‐locked loop (DLL) circuit. The proposed SPPmL interface was verified on a 65‐in. full HD (1920times1080) TFT‐LCD panel to achieve the high data transfer rate required for high‐resolution LCD models. The measured results show that the maximum data rate is higher than 2.0 Gb/s.