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P‐11: A New Five‐Mask‐Count Process for Fabrication of Poly‐Si Nanowire‐Channel CMOS Inverters
Author(s) -
Kuo ChiaHao,
Lin HorngChih,
Huang TiaoYuan
Publication year - 2012
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2012.tb05980.x
Subject(s) - fabrication , cmos , materials science , voltage , channel (broadcasting) , electrical engineering , optoelectronics , nanowire , noise (video) , process (computing) , transfer (computing) , electronic engineering , engineering , computer science , medicine , alternative medicine , pathology , artificial intelligence , image (mathematics) , parallel computing , operating system
A new five‐mask‐count process for fabricating CMOS inverters with poly‐Si NW channels is demonstrated. The fabricated devices show reasonable symmetric driving current by well‐designed structural parameters. From voltage transfer characteristics (VTC), an abrupt transition, large noise margins, and high voltage gain are obtained with a supply voltage of 5V.