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42.4: The Integrated‐Stream Protocol (iSP) Interface with Clock Embedded Scheme for the Next Generation TFT‐LCD Applications
Author(s) -
Chang RungYuan,
Huang WenChiang,
Chung ChunFan,
Ho YuHsi,
Chao ChainFu,
Yeh SzuChe,
Lyu LiRu,
Yang ChihHsiang
Publication year - 2012
Publication title -
sid symposium digest of technical papers
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.351
H-Index - 44
eISSN - 2168-0159
pISSN - 0097-966X
DOI - 10.1002/j.2168-0159.2012.tb05847.x
Subject(s) - interface (matter) , liquid crystal display , amplifier , computer science , signal (programming language) , computer hardware , chip , overhead (engineering) , embedded system , electronic engineering , electrical engineering , engineering , cmos , telecommunications , bubble , maximum bubble pressure method , parallel computing , programming language , operating system
This paper presents an integrated‐Stream Protocol (iSP) interface that is capable of high data rate operation with less signal lines for the next generation TFT‐LCD application. An 8b/9b encoding technique is employed to synchronize the system without separate clock and control signal lines, and it achieves low overhead and electromagnetic interference (EMI) performance. In order to compensate the channel attenuation, the receiver is equipped with the equalizer function. The power consumption is effectively reduced by applying the transfer‐impedance amplifier (TIA) receiver. The iSP interface has been verified on an 11.6‐inch full‐HD Chip‐On‐Glass (COG) TFT‐LCD panel with 1.35Gbps data rate. Additionally, it could be operated at higher data rate up to 1.8Gbps on Chip‐On‐Board (COB) platform.