z-logo
Premium
Preparation and characterisation of aluminium zirconium oxide for metal‐oxide‐semiconductor capacitor
Author(s) -
Quah Hock Jin,
Hassan Zainuriah,
Lim Way Foong
Publication year - 2020
Publication title -
international journal of energy research
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.808
H-Index - 95
eISSN - 1099-114X
pISSN - 0363-907X
DOI - 10.1002/er.5693
Subject(s) - tetragonal crystal system , materials science , passivation , oxide , analytical chemistry (journal) , zirconium , aluminium , dielectric , monoclinic crystal system , alloy , metal , layer (electronics) , metallurgy , crystallography , composite material , chemistry , optoelectronics , crystal structure , chromatography
Summary A functional type metal‐oxide‐semiconductor (MOS) based capacitor was fabricated and studied by using aluminium zirconium oxide (Al x Zr y O z ) as a potential high dielectric constant ( k ) gate oxide, which was transformed from as‐sputtered Al‐Zr alloy after undergoing a wet oxidation at 400°C, 600°C, 800°C, and 1000°C in the presence of nitrogen as a carrier gas. A mixture of tetragonal ZrO 2 ‐monoclinic Al x Zr y O z phases were present at 600°C while stablized tetragonal Al x Zr y O z phases were detected at higher temperatures with a minute micro strain change. The largest k value (21) was obtained by the film oxidised at 600°C, followed by 800°C while the lowest one at 1000°C. The discrepancy was due to the absence of tetragonal ZrO 2 in the latter films. The attainment of a k value closer to the reported value for ZrO 2 at 600°C suggested that the tetragonal ZrO 2 phase was one of the factors yielding a high k value at 600°C. However, further investigation was required for this sample because the slow trap density and total interface trap density was high despite a high k value, mainly attributed to the presence of negatively charged traps as the scattering centre in the film. The film obtained at 1000°C was not encourageable to be deployed as a passivation layer for Si MOS device due to its low k controlled by the thick interfacial layer.

This content is not available in your region!

Continue researching here.

Having issues? You can contact us here
Accelerating Research

Address

John Eccles House
Robert Robinson Avenue,
Oxford Science Park, Oxford
OX4 4GP, United Kingdom