Call for Papers

Due to the end of Dennard scaling and Moore’s law, complex hyper-pipelined processors are increasingly replaced by heterogeneous System-on-Chip (SoC) architectures with many specialized components. FPGA devices are becoming common targets for these systems since they allow fast turn-around time, field upgradability, and easy deployment of hardware/software solutions. To cope with the increasing complexity of such systems, designers need to raise the abstraction level from custom design flows to high-level approaches. High-level synthesis (HLS) is a popular method that allows designers to describe the functionality of a component at the software level and automatically generate the corresponding hardware description, reducing the gap between application and hardware designers. Since HLS has been making a great amount of progress and an increasing number of different application domains are pushing designers towards hardware acceleration, HLS is becoming a key enabling technology for FPGA design.