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An Equalization Time Reduction Method Using a Pseudo‐Random Number Sequence for a Cell Voltage Equalization Circuit with an LC Series Circuit
Author(s) -
SATOU DAIKI,
HOSHI NOBUKAZU
Publication year - 2016
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/eej.22869
Subject(s) - equalization (audio) , voltage , electronic circuit , electronic engineering , capacitor , series and parallel circuits , computer science , blind equalization , control theory (sociology) , engineering , electrical engineering , algorithm , decoding methods , control (management) , artificial intelligence
SUMMARY When the cells of energy storage devices such as electric double‐layer capacitors are connected in series, it results in voltage imbalance in each cell because of the nonuniform properties of the individual cells. In a previous research, the authors proposed a novel cell voltage equalization circuit using an LC series circuit, and they examined the effectiveness of this circuit. However, the characteristics of the cell voltage equalization operation depend on each cell voltage difference. Therefore, the proposed circuit has a disadvantage that the equalization time tends to be longer than other cell voltage equalization circuits with a boosting circuit. This paper proposes an equalization time reduction method that uses a pseudo‐random number sequence generated by the linear congruential generators. The proposed method can reduce the average equalization time without adding any other active or passive elements. The effectiveness of the proposed method is verified through the experimental results. According to the experimental results, the proposed equalization time reduction method reduces the equalization time to 86.5% of the conventional method.