Premium
Tamper Resistance Simulation on Algorithm Level Design
Author(s) -
Yoshikawa Masaya,
Asai Toshiya,
Shiozaki Mitsuru,
Fujino Takeshi
Publication year - 2013
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/eej.22342
Subject(s) - power analysis , side channel attack , cryptography , tamper resistance , computer science , power consumption , channel (broadcasting) , electronic circuit , algorithm , confidentiality , computer engineering , power (physics) , computer security , embedded system , engineering , computer network , electrical engineering , physics , quantum mechanics
SUMMARY Recently, side‐channel attacks have become a serious problem. These attacks estimate the secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side‐channel attacks are differential power analysis and correlation power analysis, which use the correlation between information processing and power consumption, which are related to secret keys in cryptography circuits. Therefore, new measures are required to prevent confidential information in cryptography circuits from being leaked to side‐channel information, such as power consumption. When designing preventive measures, resistance to side‐channel attacks, for instance tamper resistance, must be evaluated. This study proposes a new simulation method by which tamper resistance can be verified in the algorithm and architecture design phases. Experimental results show the validity of the proposed simulation method. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(2): 40–51, 2014; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.22342