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A hypothesis verification method using a regression tree for semiconductor yield analysis
Author(s) -
Tsuda Hidetaka,
Shirai Hidehiro,
Terabe Masahiro,
Hashimoto Kazuo,
Shinohara Ayumi
Publication year - 2013
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/eej.22334
Subject(s) - regression analysis , node (physics) , tree (set theory) , scope (computer science) , computer science , data mining , set (abstract data type) , regression , sorting , statistics , mathematics , engineering , algorithm , mathematical analysis , structural engineering , programming language
Several researchers have reported on regression tree analysis for semiconductor yield. However, the scope of these analyses is restricted by the difficulty involved in applying regression tree analysis to a small number of samples with many attributes. It is often observed that splitting attributes in the root node do not indicate the hypothesized causes of a failure. We propose a method for verifying the hypothesized causes of a failure, which reduces the number of verification hypotheses. This method involves selecting sets of analysis data with the same cause of failure, extracting the hypothesis by applying regression tree analysis separately to each set of analysis data, and merging and sorting the attributes according to the t value. The results of an experiment conducted in a real environment show that the proposed method helps in widening the scope of applicability of regression tree analysis for semiconductor yield. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 183(3): 26–36, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22334