Premium
A novel voltage clamped snubber circuit topology suitable for a multilevel inverter with lowered power loss performance
Author(s) -
Yamamoto Masayoshi,
Sato Shinji,
Nakaoka Mutsuo
Publication year - 2005
Publication title -
electrical engineering in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.136
H-Index - 28
eISSN - 1520-6416
pISSN - 0424-7760
DOI - 10.1002/eej.20015
Subject(s) - snubber , topology (electrical circuits) , voltage , electronic engineering , power (physics) , voltage source , electrical engineering , inverter , power loss , engineering , computer science , capacitor , physics , quantum mechanics
This paper presents a novel prototype of lowered loss snubber circuit topology suitable for multilevel voltage source‐inverters and rectifiers for high‐power applications. The reduced power loss characteristics and voltage capability performances of the proposed voltage clamped snubber circuit are evaluated relative to conventional RCD snubber circuits designed for four‐level voltage‐source inverters using IGBTs on the basis of experimental results. © 2004 Wiley Periodicals, Inc. Electr Eng Jpn, 150(3): 70–78, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20015