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A study on technology visualization analysis method using patent classifier
Author(s) -
Shibata Masashi,
Takahashi Masakazu
Publication year - 2021
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.12295
Subject(s) - field programmable gate array , computer science , visualization , classifier (uml) , key (lock) , artificial intelligence , enhanced data rates for gsm evolution , computer engineering , data mining , computer architecture , data science , embedded system , industrial engineering , pattern recognition (psychology) , engineering , computer security
In this paper, we propose an efficient method of technical structure analysis of Field Programmable Gate Array (FPGA) development using network analysis. Recently, with the reform of the industrial structure called “Industry 4.0″ and the explosive expansion of the application area of Artificial Intelligence (AI), the demand for computing power in edge devices is increasing. For these backgrounds, the acceleration by FPGA is focused on the industry. Hence, in this paper, we analyze the technology development trends of a significant FPGA supplier. As analytical data, we employ patents obtained by the company in the U.S. We focus on the classifiers in the patent information. We create graphs by classifiers and analyze their clusters. From the results of extracting graph features by the proposed method, key technology areas and their transitions are revealed in the technology development of FPGA suppliers.