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A design of EEGNet‐based inference processor for pattern recognition of EEG using FPGA
Author(s) -
Tsukahara Akihiko,
Anzai Yuki,
Tanaka Keita,
Uchikawa Yoshinori
Publication year - 2021
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.12280
Subject(s) - field programmable gate array , computer science , electroencephalography , brain–computer interface , gate array , interface (matter) , mechatronics , state (computer science) , embedded system , field (mathematics) , computer hardware , computer architecture , artificial intelligence , parallel computing , algorithm , psychology , mathematics , bubble , maximum bubble pressure method , psychiatry , pure mathematics
Abstract In recent years, brain‐machine interface (BMI) is attracting attention. BMI is a technology that enables machine operation using biological signals such as EEG. For further advancement of BMI technology, there is a need for advanced BMI devices. Therefore, the purpose of this study is development of BMI hardware specialized for handling EEG as an interface for human adaptive mechatronics (HAM) that know human's state and operate according to the state. As one of the examinations, we are constructing a pattern recognition processor for EEG in real time on Field Programmable Gate Array (FPGA), which is an LSI that can reconfigure the processor. This paper reports on the designed EEGNet processor and the result of logic circuit simulation and implementation.