Premium
Voltage balancing control based on gate signal delay in series connection of SiC‐MOSFET
Author(s) -
Shingu Katsuya,
Wada Keiji
Publication year - 2019
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.12165
Subject(s) - chopper , electrical engineering , series and parallel circuits , voltage , mosfet , electronic engineering , voltage regulation , overdrive voltage , computer science , voltage divider , voltage optimisation , engineering , transistor
Recently, research and development of SiC power devices have been done, and SiC power devices have become commercially available. The SiC power devices are suitable for realizing to medium voltage applications. Since, the voltage rating of commercial power devices is limited to less than 1.2 kV, they should be connected in series to maintain a higher voltage rating. However parasitic parameters of these devices are not the same, and therefore the voltage sharing during turn‐off operations cannot be controlled. This article proposes a digital control for the voltage balancing of series connected SiC‐MOSFETs during turn‐off operations. In order to compensate the voltage unbalance conditions, this article presents a time‐adjustment gate‐drive circuit using a digital delay line; experimental results for the feedback control using a buck chopper circuit are also presented.