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A Serial Processing FIR Inverse Filter Circuit
Author(s) -
TAKATO KENJI
Publication year - 2015
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11761
Subject(s) - filter design , raised cosine filter , root raised cosine filter , adaptive filter , finite impulse response , inverse filter , infinite impulse response , computer science , low pass filter , algorithm , control theory (sociology) , mathematics , filter (signal processing) , digital filter , butterworth filter , 2d filters , kernel adaptive filter , prototype filter , inverse , artificial intelligence , geometry , control (management) , computer vision
SUMMARY Inverse filters are used in many fields, including audio circuits, metal and optical telecom line equalization, and wireless equalization. The purpose of such filters is to compensate for distortion in the signal caused by the transmission medium. Design methods for an inverse filter using an IIR filter, FFT/IFFT, and an adaptive FIR filter are available. However, an IIR filter has some problems as regards stability. The FFT/IFFT method requires significant calculation and the adaptive FIR filter needs substantial time. This paper proposes a new method of generating the FIR inverse filter coefficients through serial calculations of the impulse response and its expected value. At first, all coefficients of the FIR filter except the first are set to zero. When an input of the impulse response data X N is applied to the filter, the temporal output of the FIR filter W N is compared to the expectation value E N , and the FIR inverse filter coefficients g N are calculated usingg N = ( E N − W N ) X ostep by step. This algorithm is simulated by calculations in Excel. The FPGA circuit is synthesized using VHDL and a behavior model is simulated using the ISE design tool. The coefficients of the filter are generated during the input period of the data X N . Therefore, real‐time inverse filter circuit generation is possible.