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Design Technology of Stacked‐Type Chain PRAM
Author(s) -
Kato Sho,
Watanabe Shigeyoshi
Publication year - 2015
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11641
Subject(s) - ferroelectric ram , computer science , non volatile memory , nand gate , semiconductor memory , non volatile random access memory , transistor , sense amplifier , memory cell , scalability , flash memory , computer hardware , memory refresh , electronic engineering , computer memory , logic gate , electrical engineering , capacitor , engineering , voltage , algorithm , database
SUMMARY A stacked‐type chain PRAM that can result in lower cost than flash memory has been proposed. The newly proposed memory cell uses a PCM for data storage and an MOS transistor connected in parallel. This memory cell is connected in series to realize the chain structure. The cell structure, the design method for realizing stable read and write operation, and the core circuit for the stacked‐type chain PRAM are described. The newly proposed memory cell has been designed to use BiCS (Bit Cost Scalable) process technology in order to achieve low‐cost memory. The design of the resistance of the PCM and the pass transistor is a key issue for realizing stable operation. To design the row decoder, the circuit concept of stacked ferroelectric RAM (FeRAM) with an NAND structure cell has been successfully adopted with SGT. The newly proposed stacked‐type chain PRAM is a promising candidate for realizing high‐speed and low‐power future nonvolatile semiconductor memory.