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A Study of Self‐Dithering for Δ Σ Fractional‐N PLL
Author(s) -
Kato Yuji,
Ioka Eri,
Matsuya Yasuyuki
Publication year - 2015
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11606
Subject(s) - dither , phase locked loop , control theory (sociology) , oscillation (cell signaling) , spurious relationship , signal (programming language) , limit cycle , limit (mathematics) , mathematics , physics , electronic engineering , computer science , phase noise , engineering , mathematical analysis , noise shaping , statistics , control (management) , artificial intelligence , biology , programming language , genetics
SUMMARY The Δ Σ fractional‐N phase‐locked loops (PLL) are being investigated in order to realize a low fractional spurious signal characteristic. In this PLL, the Δ Σ modulator sets the fractional division ratio. However, a limit cycle oscillation occurs in the Δ Σ modulator when the input value is fixed, and as a result, the limit cycle oscillation increases the spurious signal power. Therefore, a method is required to suppress this oscillation. In this paper, we propose a self‐dithering Δ Σ fractional‐N PLL that inhibits the limit cycle oscillation without an external dither generating circuit. The proposed circuit generates dither from the internal signals of the PLL. We simulated the output spectrum of the proposed circuit. The results showed that the proposed circuit suppressed limit cycle oscillation, and that the spurious level of the proposed circuit was almost equal to the spurious level without limit cycle oscillation.