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Design Technology of Stacked Type DTMOS
Author(s) -
Hiroshima Yu,
Kodama Takahiro,
Watanabe Shigeyoshi
Publication year - 2014
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11584
Subject(s) - nmos logic , pmos logic , dram , nand gate , materials science , mosfet , inverter , electronic engineering , substrate (aquarium) , transistor , logic gate , electrical engineering , optoelectronics , computer science , engineering , voltage , oceanography , geology
SUMMARY Stacked type DTMOS, which makes it possible to realize both the high‐speed, low‐power characteristics of FinFET type DTMOS and small the pattern area of stacked transistors, has been newly proposed. The delay time of the substrate of stacked type DTMOS can be reduced to less than 10% of that for conventional FinFET type DTMOS by using the sidewall connection between the gate and substrate. By using a stacked structure of NMOS with a (110) substrate on PMOS with a (100) substrate, high‐speed performance with optimized mobility value can be realized without sacrificing the pattern area. Furthermore, the pattern area of the inverter/NAND circuit, LSI for communication, and the DRAM buffer circuit with stacked type DTMOS is compared with that of conventional FinFET type DTMOS. The newly proposed stacked type DTMOS is a promising candidate for realizing high‐performance system LSI such as GHz class microprocessors.