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A Circuit Design Method for Dynamic Reconfigurable Circuits
Author(s) -
Sawano Hajime,
Kambe Takashi
Publication year - 2014
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11577
Subject(s) - computer science , granularity , encoder , computer architecture , routing (electronic design automation) , electronic circuit , circuit design , reconfigurable computing , embedded system , electronic engineering , design methods , computer hardware , field programmable gate array , computer engineering , engineering , electrical engineering , mechanical engineering , operating system
Summary Reconfigurable computing (RC) is a new paradigm that addresses the conflicting design requirements of high performance and high area density. Coarse‐grained architecture RC (CGA‐RC) operates at the word level of granularity and exhibits better power and performance features than fine‐grained architectures. However, in a CGA‐RC system, the processing elements (PE) implement several types of arithmetic operations and the routing between them has a fixed architecture. To achieve both good performance and high PE utilization for all applications, this paper proposes an interactive circuit design methodology for dynamically reconfigurable processors to accelerate their performance and achieve compact circuits. The method is applied to a JPEG encoder design and its performance evaluated.