Premium
Design of a high‐speed‐sampling stochastic flash analog‐to‐digital converter using device mismatch
Author(s) -
Ham Hyunju,
Matsuoka Toshimasa,
Wang Jun,
Taniguchi Kenji
Publication year - 2013
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.11411
Subject(s) - spurious free dynamic range , comparator , flash adc , analog to digital converter , quantization (signal processing) , electronic engineering , offset (computer science) , cmos , integral nonlinearity , successive approximation adc , computer science , sampling (signal processing) , flash (photography) , differential nonlinearity , electrical engineering , engineering , physics , converters , voltage , algorithm , detector , optics , programming language
Abstract A stochastic flash analog‐to‐digital converter (SF‐ADC) utilizing device mismatch is designed using a 65‐nm CMOS process. Since the proposed SF‐ADC uses thresholds determined by the input‐referred comparator offsets, large input‐referred offsets are allowed. The quantization error and nonlinearity of SF‐ADC are demonstrated, and the input range is enlarged by using nonlinearity reduction technique. At 1.6 GS/s sampling, the designed ADC achieves 34.7‐dB SFDR and 29.0‐dB SNDR without any calibration circuits despite the large input‐referred offset of 102 mV. At this conversion speed, it consumes 134 mW with a 1.2‐V power supply. © 2012 Wiley Periodicals, Inc. Electron Comm Jpn, 96(1): 51–62, 2013; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/ecj.11411