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Vertical double‐gate MOSFET device technology
Author(s) -
Masahara Meishoku,
Liu Yongxun,
Endo Kazuhiko,
Matsukawa Takashi,
Suzuki Eiichi
Publication year - 2008
Publication title -
electronics and communications in japan
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.131
H-Index - 13
eISSN - 1942-9541
pISSN - 1942-9533
DOI - 10.1002/ecj.10021
Subject(s) - mosfet , electrical engineering , short channel effect , cmos , electronic engineering , logic gate , scalability , power (physics) , threshold voltage , computer science , engineering , voltage , transistor , physics , quantum mechanics , database
Silicon device technology is facing several difficulties. Especially, explosion of power consumption due to short‐channel effects (SCEs) becomes the biggest issue in further device scaling down. Fortunately, double‐gate (DG) MOSFETs have promising potential to overcome this obstacle. The DG‐MOSFET is recognized to be the most scalable MOSFET for its high SCE immunity. In addition, independent DG‐MOSFET (4T‐DG‐MOSFET) has great advantage to enable the threshold voltage control for the flexible power management. Through this work, we have realized ideal DG‐MOSFETs using newly developed vertical DG‐MOSFET device technology. This article examines the effectiveness of the vertical DG‐MOSFETs in future high‐performance and ultralow‐power CMOS circuits. © 2008 Wiley Periodicals, Inc. Electron Comm Jpn, 91(1): 46– 51, 2008; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.10021