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Decoupled parallel hierarchical matching schedulers
Author(s) -
GonzálezCastaño F. J.,
LópezBravo C.,
RodelgoLacruz M.,
AsoreyCacheda R.
Publication year - 2007
Publication title -
international journal of communication systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.344
H-Index - 49
eISSN - 1099-1131
pISSN - 1074-5351
DOI - 10.1002/dac.828
Subject(s) - computer science , network packet , von neumann architecture , matching (statistics) , packet switching , controller (irrigation) , power (physics) , parallel computing , algorithm , computer network , mathematics , statistics , agronomy , biology , operating system , physics , quantum mechanics
The load balanced Birkhoff–von Neumann switch is an elegant VOQ architecture with two outstanding characteristics: (i) it has a computational cost of O (1) iterations and (ii) input controllers do not exchange information (as a result, it allows decoupled implementations with a low power density). The load balancing stage guarantees stability under a broad class of traffic patterns. It may alter packet sequence, but this can be solved with appropriate packet selection strategies. The average packet delay caused by previous maximal size matching algorithms, such as iSLIP, RDSRR, or PHM is noticeably lower than that of a Birkhoff–von Neumann switch, especially for low and medium loads. However, they need tightly coupled VOQ controllers, which implies higher power density. For example, this makes difficult to apply those algorithms to optical switching architectures. Moreover, they require O (log 2 N ) iterations to converge, and this computational cost may be unacceptable for the slot lengths in optical packet switches. In this paper, we propose a family of decoupled Parallel Hierarchical Matching (PHM) VOQ controllers (DPHM). They outperform the Birkhoff–von Neumann scheduler, which can be viewed as a member of the family (in fact, the simplest one). DPHM schedulers have a computational cost of O (1) iterations and, unlike last generation maximal size matching algorithms, they allow a low input controller interconnection complexity (low power density switch implementation). Copyright © 2006 John Wiley & Sons, Ltd.

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