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A multistage ATM switch with interstage buffers
Author(s) -
Kim Hyong Sok,
LeonGarcia Alberto
Publication year - 1989
Publication title -
international journal of digital and analog cabled systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.344
H-Index - 49
eISSN - 1099-1131
pISSN - 0894-3222
DOI - 10.1002/dac.4520020412
Subject(s) - computer science , queueing theory , computer network , network packet , asynchronous transfer mode , latency (audio) , asynchronous communication , throughput , packet switching , real time computing , telecommunications , wireless
Abstract Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability. 1‐8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self‐routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed‐up. The switch has log 2 N stages that forward packets in a store‐and‐forward fashion, thus incurring a latency of log 2 N time periods. Performance analysis shows that the additional delay is small.