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ATM switches—basic architectures and their performance
Author(s) -
Rathgeb Erwin P.,
Theimer Thomas H.,
Huber Manfred N.
Publication year - 1989
Publication title -
international journal of digital and analog cabled systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.344
H-Index - 49
eISSN - 1099-1131
pISSN - 0894-3222
DOI - 10.1002/dac.4520020405
Subject(s) - computer science , node (physics) , broadband integrated services digital network , interconnection , broadband , asynchronous transfer mode , path (computing) , computer network , broadband networks , distributed computing , topology (electrical circuits) , telecommunications , engineering , electrical engineering , structural engineering
The prospect of a broadband ISDN based on the ATM principle has stimulated the development of new, high‐performance switching node architectures. In this paper different options for the switching networks used in such a node will be discussed in some detail. First, some generic architectures for the individual switching elements will be presented including the aspects of buffering and collision resolution, followed by a short classification of different types of switching networks and some performance figures for delta networks, a class of multi‐stage, single‐path interconnection networks. In the last section, the sensitivity of the performance results with respect to the traffic assumptions will be discussed.