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Comparison of ATM switching architectures
Author(s) -
Wulleman Raymond,
van Landegem Thierry
Publication year - 1989
Publication title -
international journal of digital and analog cabled systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.344
H-Index - 49
eISSN - 1099-1131
pISSN - 0894-3222
DOI - 10.1002/dac.4520020404
Subject(s) - cut through switching , asynchronous transfer mode , broadband integrated services digital network , computer science , fast packet switching , label switching , circuit switching , computer network , connectionless communication , atm adaptation layer , node (physics) , lan switching , packet switching , broadband networks , jitter , integrated services digital network , burst switching , broadband , network packet , multiprotocol label switching , transmission delay , quality of service , telecommunications , processing delay , engineering , structural engineering
Clear examination of work currently done within CCITT indicates the importance of a broadband telecommunication network. As this network should be capable of integrating all services in an efficient way—in order to reduce cost—the asynchronous transfer mode (ATM) was selected by CCITT as the target transfer mode for implementing the broadband integrated services digital network (BISDN). This selection implies that the switching nodes in the BISDN network are capable of supporting this high‐speed packet and connection‐orientated technique. Within the literature different switching node architectures based upon ATM have been proposed. All of these architectures should meet the high‐speed and high‐throughput requirements so as to cope with the delay and jitter performance objectives. In a first step this paper describes alternative switching techniques for the basic building block (switching element) of a switching node. A common model architecture of the switching element is drafted. A classification of switching elements described in the literature is derived and the influence on the complexity and performance is weighted. In a second step the switching node architecture is further elaborated according to the control and flexibility requirements. Core (switching) and edge (switching related) functions are listed, and possible functional partitionings are discussed. Finally, these ATM switching architectures are compared according to a background frame consisting of several straightforward comparison points such as the buffering strategy, the internal routeing method, the switching overhead, the connection‐orientated or connectionless operation, etc.