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FPGA implementation of highly secure, hardware‐efficient QC‐LDPC code–based nonlinear cryptosystem for wireless sensor networks
Author(s) -
Stuart Celine Mary,
Deepthi P. P.
Publication year - 2016
Publication title -
international journal of communication systems
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.344
H-Index - 49
eISSN - 1099-1131
pISSN - 1074-5351
DOI - 10.1002/dac.3233
Subject(s) - computer science , field programmable gate array , cryptography , cryptosystem , computer hardware , hardware architecture , key (lock) , embedded system , computer engineering , algorithm , software , computer security , programming language
Summary This paper presents the design and implementation of an integrated architecture for embedding security into quasi‐cyclic (QC) low‐density parity‐check (LDPC) code–based cryptographic system through a nonlinear function of low hardware complexity. Instead of using standard S ‐boxes for implementation of nonlinear function, this paper considers a method on the basis of maximum length cellular automata (CA), so that enhanced security can be achieved with simple hardware structure. The proposed system adopts a lightweight random bit stream generator on the basis of linear feedback shift register (LFSR) for generating random error vectors, so that a large number of vectors with very good cryptographic properties can be made available with low hardware cost. Different permutation patterns generated for different message blocks help to provide good degrees of freedom for tuning security with reasonable key size. The hardware architecture for the proposed system is developed and validated through implementation on Xilinx Spartan 3S500E. Analytical and synthesis results show that the proposed scheme is lightweight and offers very high security through continuously changing parameters, thus making it highly suitable for resource‐constrained applications.