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Modern Applications of Plasma Etching and Patterning in Silicon Process Technology
Author(s) -
Engelhardt M.
Publication year - 1999
Publication title -
contributions to plasma physics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.531
H-Index - 47
eISSN - 1521-3986
pISSN - 0863-1042
DOI - 10.1002/ctpp.2150390509
Subject(s) - resist , materials science , wafer , plasma etching , reactive ion etching , etching (microfabrication) , fabrication , dram , deep reactive ion etching , chemical mechanical planarization , dry etching , optoelectronics , plasma , silicon , nanotechnology , layer (electronics) , medicine , alternative medicine , physics , pathology , quantum mechanics
Besides plasma etching of through‐wafer interconnects in wafer stacks for vertical integration of chips, fabrication of platinum (Pt) electrodes with non‐tapered sidewalls for the storage node in modern memories (DRAMs and FeRAMs) is one of the most challenging tasks of plasma process technology today. This paper describes the achievement of vertical integration of chips by plasma etching of high aspect ratio interchip vias. The etching processes for dielectrics, single crystal silicon, and the organic glue layer were all optimized for minimum reactive ion etching (RIE) lag i.e. for minimum decrease of etch rate with increasing etch depth. Furthermore the fabrication of perfect Pt electrodes for modern DRAMs and FeRAMs is reported. Vertical Pt profiles were achieved by plasma processing with resist mask. In this novel approach, the build‐up of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the pre‐etch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.