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Performance Analysis of Reversed Binary Decision Diagram Pass Transistor Logic Synthesis
Author(s) -
Bhuvaneswari Thangavel,
Prasad Vishnuvajjula,
Singh Ajay Kumar,
Senthilpari Chinnaiyan
Publication year - 2013
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.822
Subject(s) - binary decision diagram , boolean function , dissipation , electronic circuit , multiplexer , computer science , benchmark (surveying) , binary number , algorithm , and inverter graph , representation (politics) , boolean circuit , logic gate , mathematics , arithmetic , electrical engineering , engineering , physics , multiplexing , telecommunications , geodesy , politics , law , geography , political science , thermodynamics
SUMMARY Binary decision diagrams (BDDs) are the most frequently used data structure for the representation and handling of Boolean functions because of their excellent time and space efficiencies. In this article, a reversed BDD‐based pass transistor logic (PTL) logic synthesis is presented for low‐power and high‐performance circuits without exploiting the canonical property of BDDs. The procedure of the reversed BDD transformation into PTL is achieved by a one‐to‐one correspondence with the BDD node and PTL cell. Layouts are generated for the benchmark circuits and simulated in terms of power dissipation, propagation delay and area. The reversed BDD technique performs better in terms of area, delay and power dissipation due to the regularity, a reduced critical path, less interconnection wires, a multiplexer‐based construction of PTL circuits, and less switching activities. Copyright © 2011 John Wiley & Sons, Ltd.