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Analysis of multi‐gigabits signal integrity through clock H‐tree
Author(s) -
Eudes Thomas,
Ravelo Blaise
Publication year - 2013
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.818
Subject(s) - interconnection , computer science , bottleneck , electronic engineering , signal integrity , tree (set theory) , clock rate , clock skew , signal (programming language) , clock signal , engineering , embedded system , telecommunications , jitter , chip , programming language , mathematical analysis , mathematics
The H‐tree interconnect network is frequently used for the clock signal sharing in the microelectronic systems. Due to the increase of complexity and operating processing data speed, these interconnect effects can bottleneck the technological advancement. Hence, more accurate interconnect modelling methods are necessary for electronic designers. For this reason, a simple and accurate ultra‐wide band (UWB) model of multilevel distributed interconnection clock trees as a single input multiple outputs (SIMO) system is developed in this article. Very accurate single input single output (SISO) model transfer functions are derived. This method allows the signal integrity prediction regarding the distributed H‐tree characteristics including the source and load impedances. In order to demonstrate the relevance of model developed, analyses of two‐ and three‐level tree networks were performed. Distributed H‐tree realistic devices formed by sub‐millimetre physical length lines for applications for standardised Printed Circuit Board (PCB) interconnections were experimented numerically. The piece of lines constituting the trees is modelled by UWB RLCG network from DC to 8 GHz which takes into account the frequency dispersions and dielectric loss effects. Thus, excellent correlations between simulations and the results from the models proposed were observed both in frequency and time domains regarding 2.5 Gbits/s clock input. Copyright © 2012 John Wiley & Sons, Ltd.