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Design space exploration for sparse matrix‐matrix multiplication on FPGAs
Author(s) -
Lin Colin Yu,
Wong Ngai,
So Hayden KwokHay
Publication year - 2013
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.796
Subject(s) - matrix multiplication , computer science , block (permutation group theory) , matrix (chemical analysis) , field programmable gate array , multiplication (music) , sparse matrix , design space exploration , parallel computing , block size , energy (signal processing) , algorithm , mathematics , embedded system , key (lock) , statistics , physics , geometry , materials science , computer security , quantum mechanics , combinatorics , composite material , quantum , gaussian
SUMMARY The design and implementation of a sparse matrix‐matrix multiplication architecture on field‐programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power‐delay and energy‐delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user‐tunable power‐delay and energy‐delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on‐chip computational architecture for different system power‐delay and energy‐delay requirements. It is in contrast to conventional dense matrix‐matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power‐delay product favors less PEs and smaller block size for the 90%‐sparsity matrix‐matrix multiplications. Although in order to achieve better energy‐delay product, more PEs and larger block size are preferred. Copyright © 2011 John Wiley & Sons, Ltd.