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VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
Author(s) -
Sun ChiChia,
Donner Philipp,
Götze Jürgen
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.774
Subject(s) - cordic , discrete cosine transform , computer science , integer (computer science) , very large scale integration , codec , application specific integrated circuit , transformation (genetics) , mpeg 2 , parallel computing , arithmetic , algorithm , computer hardware , computer architecture , field programmable gate array , embedded system , image (mathematics) , mathematics , artificial intelligence , biochemistry , chemistry , gene , programming language
SUMMARY In this paper, a low‐complexity and highly integrated IP Core for image/video transformations is presented. It can perform quantized 8×8 DCT and quantized 8 × 8/4 × 4 H.264 integer transforms on the presented configurable architecture using integer shift–add arithmetic operations. The MPEG‐4/H.264 experimental and circuit simulation results show that the reconfigurable modules and the CORDIC‐Scaler can not only approximate the arbitrary scaling values for different video standards efficiently but also achieve very high throughput and retain good transformation quality compared with the default methods in terms of PSNR. Therefore, the proposed IP Core is very suitable for low‐complexity multi‐purpose Video Codecs in SoC designs. Copyright © 2011 John Wiley & Sons, Ltd.