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From energy‐delay metrics to constraints on the design of digital circuits
Author(s) -
Alioto Massimo,
Consoli Elio,
Palumbo Gaetano
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.757
Subject(s) - cmos , computer science , electronic circuit , digital electronics , electronic engineering , range (aeronautics) , circuit design , energy (signal processing) , physical design , integrated circuit design , computer engineering , reliability engineering , electrical engineering , engineering , embedded system , mathematics , statistics , aerospace engineering
SUMMARY In this paper, the adoption of general metrics of the energy‐delay tradeoff is investigated to achieve energy‐efficient design of digital CMOS very large‐scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of E i D j metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing E i D j metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65‐nm CMOS technology are also reported to exemplify the theoretical results. Copyright © 2011 John Wiley & Sons, Ltd.