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A new efficient SC integrator scheme for high‐speed low‐power applications
Author(s) -
Amoroso F. A.,
Pugliese A.,
Cappuccino G.
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.749
Subject(s) - integrator , passive integrator circuit , integrating adc , op amp integrator , cmos , settling time , capacitor , electronic engineering , network topology , topology (electrical circuits) , power (physics) , computer science , switched capacitor , control theory (sociology) , voltage , engineering , electrical engineering , operational amplifier , rc circuit , control engineering , physics , amplifier , step response , ćuk converter , quantum mechanics , artificial intelligence , operating system , control (management)
SUMMARY A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35−µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.