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Three novel improved CMOS C‐multipliers
Author(s) -
AguadoRuiz Jesus,
LopezMartin Antonio J.,
RamirezAngulo Jaime
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.745
Subject(s) - current mirror , cascode , current conveyor , cmos , current (fluid) , electronic engineering , capacitance , network topology , electrical engineering , computer science , chip , topology (electrical circuits) , current source , engineering , voltage , transistor , physics , resistor , amplifier , electrode , quantum mechanics , operating system
SUMMARY Three novel improved CMOS capacitance scaling schemes are presented and compared with some conventional schemes. The novel topologies that use a modified second‐generation current conveyor, an improved cascode current mirror and an OTA with two outputs connected in current steering configuration provide higher values of Q and better frequency responses than conventional structures using basic current mirror schemes, as the simple current mirror or cascode current mirrors. Simulation results and some measurements of a chip prototype are presented. Copyright © 2011 John Wiley & Sons, Ltd.