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Energy‐efficient single‐clock‐cycle binary comparator
Author(s) -
Frustaci Fabio,
Perri Stefania,
Lanuzza Marco,
Corsonello Pasquale
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.720
Subject(s) - comparator , dissipation , cmos , power (physics) , binary number , clock rate , computer science , energy (signal processing) , electronic engineering , electrical engineering , engineering , physics , mathematics , voltage , arithmetic , quantum mechanics , thermodynamics
SUMMARY A new fast low‐power single‐clock‐cycle binary comparator is presented. High speed is assured by using parallel‐prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.