Premium
A 120–420 MHz delay‐locked loop with multi‐band voltage‐controlled delay unit
Author(s) -
Kuo KoChi,
Hsu YiHsi
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.705
Subject(s) - jitter , delay locked loop , voltage , cmos , sensitivity (control systems) , dissipation , power (physics) , physics , noise (video) , electronic engineering , electrical engineering , phase locked loop , computer science , optoelectronics , engineering , quantum mechanics , artificial intelligence , image (mathematics) , thermodynamics
SUMMARY A low‐jitter and low‐power dissipation delay‐locked loop (DLL) is presented. A proposed multi‐band voltage control delay unit (MVCDU) is employed to extend the operation frequency of the DLL by controlling the delay cell within the MVCDU. The jitter of DLL is reduced due to MVCDU's low sensitivity. The delay cell in the MVCDU employs a differential configuration to further reduce the noise impact from the fluctuation in the supply and ground voltage. The operating frequency of the proposed DLL ranges from 120 to 420 MHz. The proposed design has been fabricated in a TSMC 0.18µm CMOS process. The measured RMS and peak‐to‐peak jitters are 4.86 and 34.55 ps, respectively, at an operating frequency of 300 MHz. The power dissipation is below 14.85 mW at an operating frequency of 420 MHz. Copyright © 2010 John Wiley & Sons, Ltd.