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An accurate power delivery system (PDS) design methodology for high‐speed digital systems
Author(s) -
Nabil Shaymaa M.,
ElRouby Alaa B.,
Khalil Ahmed H.
Publication year - 2012
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.704
Subject(s) - decoupling capacitor , decoupling (probability) , capacitor , voltage , capacitance , electronic engineering , computer science , power integrity , power (physics) , design methods , electrical engineering , engineering , control engineering , signal integrity , printed circuit board , mechanical engineering , chemistry , physics , electrode , quantum mechanics
SUMMARY The trend in high‐speed digital circuits is to increase speed and density and to operate at lower voltage. This fast increase in the switching speed combined with the decrease of the operating voltage causes the allowable absolute voltage variations to decrease, which makes the PDS design a more challenging task than ever. Moreover, the complex 3D nature of the modern PDS causes it to be more sensitive to capacitors' placement as well as capacitance value. In this paper, we introduce an efficient complete solution for the design of high‐speed digital PDS. This solution (a) takes the effects of the decoupling capacitor placement into consideration through a 3D electromagnetic simulation of the PDS, (b) defines a more‐realistic PDS design target, and (c) presents a clear capacitor value selection methodology. Finally, we applied our methodology to an industrial test case, compared its results with that of industrial design, and showed its advantages. Copyright © 2010 John Wiley & Sons, Ltd.