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On the simulation of fast settling charge pump PLLs up to fourth order
Author(s) -
Guermandi Marco,
Franchi Eleonora,
Gnudi Antonio
Publication year - 2011
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.700
Subject(s) - settling time , phase locked loop , time domain , charge pump , frequency domain , phase noise , electronic engineering , control theory (sociology) , pll multibit , noise (video) , computer science , settling , transfer function , algorithm , engineering , voltage , electrical engineering , step response , control engineering , artificial intelligence , environmental engineering , image (mathematics) , computer vision , capacitor , control (management)
In this paper, we discuss three different models for the simulation of integer‐N charge‐pump phase‐locked loops (PLLs), namely the continuous‐time s‐domain and discrete time z‐domain approximations and the exact semi‐analytical time‐domain model. The limitations of the two approximated models are analyzed in terms of error in the computed settling time as a function of loop parameters, deriving practical conditions under which the different models are reliable for fast settling PLLs up to fourth order. Besides, output spectral purity analysis methods based upon the time‐domain model are introduced and the results are compared with those obtained by means of the s‐domain model in terms of phase noise and reference spur estimation. As a case study, we use the three models to analyze a fast switching PLL to be integrated in a frequency synthesizer for WiMedia MB‐OFDM UWB systems. Copyright © 2010 John Wiley & Sons, Ltd.