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Design criterion for high‐speed low‐power SC circuits
Author(s) -
Amoroso F. A.,
Pugliese A.,
Cappuccino G.
Publication year - 2011
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.687
Subject(s) - settling time , settling , switched capacitor , electronic circuit , electronic engineering , cmos , capacitance , computer science , capacitor , operational amplifier , capacitive sensing , amplifier , electrical engineering , engineering , control engineering , voltage , physics , step response , electrode , quantum mechanics , environmental engineering
The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.