Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array | Zendy

Lopich Alexey | Zendy; Dudek Piotr | Zendy

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Asynchronous cellular logic network as a co‐processor for a general‐purpose massively parallel array

Author(s) -

Lopich Alexey,

Dudek Piotr

Publication year - 2011

Publication title -

international journal of circuit theory and applications

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.364

H-Index - 52

eISSN - 1097-007X

pISSN - 0098-9886

DOI - 10.1002/cta.679

Subject(s) - asynchronous communication , massively parallel , computer science , pixel , computer hardware , binary number , process (computing) , cmos , asynchronous circuit , parallel computing , power (physics) , object (grammar) , electronic engineering , telecommunications , engineering , synchronous circuit , arithmetic , artificial intelligence , physics , mathematics , quantum mechanics , clock signal , jitter , operating system

This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger‐wave propagations, extensively used in various image‐processing algorithms. The circuit operates in a continuous‐time mode, achieving high operational performance and low‐power consumption. An integrated circuit with proof‐of‐concept array of 24×60 cells has been fabricated in a 0.35µm three‐metal CMOS process and tested. Occupying only 16×8µm 2 the binary wave‐propagation cell is designed to be used as a co‐processor in general‐purpose processor‐per‐pixel arrays intended for focal‐plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.

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