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Improving Networks‐on‐Chip performability: A topology‐based approach
Author(s) -
Elmiligi Haytham,
Morgan Ahmed A.,
ElKharashi M. Watheq,
Gebali Fayez
Publication year - 2011
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.662
Subject(s) - computer science , network topology , metric (unit) , topology (electrical circuits) , performance metric , logical topology , power (physics) , embedded system , computer network , engineering , operations management , electrical engineering , management , quantum mechanics , economics , physics
The performability metric is commonly used in Networks‐on‐Chip (NoC)‐based systems to represent their abilities to successfully complete specific tasks in finite time intervals. In this paper, we present a novel topology‐based performability model for NoC‐based systems. The model is used to evaluate the performability of NoC‐based systems at early design phases. A comparative study of nine commonly used network architectures is performed using the proposed model. The purpose of the study is to explore the impact of the network topology on the performability of NoC‐based systems. Using the output from this study, a new methodology is proposed to improve the performability of a given application at early design phases. In this methodology, a joint consideration of five design parameters (network topology, target application traffic distribution, mapping of processing elements, noise power, and voltage swing) is carried out. Using the proposed methodology, designers can select the optimal topology for a given application that maximizes system performability. The effectiveness of the proposed methodology in determining the optimal topology is verified by experimental work and validated through a case study of a video application. Copyright © 2010 John Wiley & Sons, Ltd.