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On IIR‐based bit‐stream multipliers
Author(s) -
Ng ChiuWa,
Wong Ngai,
So Hayden KwokHay,
Ng TungSang
Publication year - 2011
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.623
Subject(s) - multiplier (economics) , infinite impulse response , computer science , linearity , key (lock) , noise (video) , algorithm , electronic engineering , selection (genetic algorithm) , arithmetic , digital filter , mathematics , bandwidth (computing) , telecommunications , engineering , artificial intelligence , computer security , economics , image (mathematics) , macroeconomics
We analyze the existing bi‐level IIR‐based bit‐stream multiplier and propose selection criteria for the key design parameter governing droop and phase linearity. Based on the proposed choice of parameter, we then extend the bi‐level design to tri‐ and quad‐level architectures that offer better signal‐to‐noise performance. Hardware complexity and noise performance of these designs are also contrasted with previously proposed FIR‐based bit‐stream multipliers. Useful design guidelines are subsequently drawn. Copyright © 2010 John Wiley & Sons, Ltd.