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Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations
Author(s) -
Storace Marco,
Poggi Tomaso
Publication year - 2011
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.610
Subject(s) - realization (probability) , field programmable gate array , benchmark (surveying) , computer science , piecewise linear function , piecewise , representation (politics) , function (biology) , algorithm , random variate , parallel computing , mathematics , computer hardware , statistics , geometry , geodesy , evolutionary biology , politics , political science , law , biology , geography , random variable , mathematical analysis
Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n ‐dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three‐variate static functions and one concerning a dynamical control system defined by a bi‐variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.