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T1/E1/J1 receiver in CMOS
Author(s) -
Sobot Robert,
Guo Haizheng
Publication year - 2009
Publication title -
international journal of circuit theory and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.364
H-Index - 52
eISSN - 1097-007X
pISSN - 0098-9886
DOI - 10.1002/cta.546
Subject(s) - cmos , chip , signal (programming language) , power (physics) , electrical engineering , electronic engineering , engineering , radio receiver design , computer science , physics , channel (broadcasting) , transmitter , quantum mechanics , programming language
Behavioural model, simulation and testing results of a mixed‐signal short‐/long‐haul receiver suitable for high‐speed T1/E1/J1 application in CMOS are presented. The measured results demonstrate successful recovery of distorted incoming signals attenuated from 0 to 44 dB (max). The mixed‐signal part of the receiver chip occupies area of 1.2 mm × 1.8 mm in CMOS 0.35 µm process and requires typically 120 mW of power at 3.3 V power supply. Digital framer supports the operation of the receiver whereas local RAM is used for storing the unshielded twisted pair cable models that can be easily reprogrammed. Copyright © 2008 John Wiley & Sons, Ltd.
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